/* (c)INRIA 1999 Christophe.Lavarenne@inria.fr */
/* $Id: C40.ld,v 1.1 2000/04/17 13:01:34 lavarenn Exp $ */
/* ----------- Linker command file --------- */
/* compiler options: -v40 -mb */
-c             /* linking with C conventions */
-stack 128     /* C call stack */
-heap  128     /* C heap for malloc */
-lrts40.lib    /* runtime support */

MEMORY{
  ROM:    org=0x00000000, len=0x00001000 /*   4K internal ROM boot    */
  RAM0:   org=0x002FF800, len=0x00000400 /*   1K internal RAM block 0 */
  RAM1:   org=0x002FFC00, len=0x00000400 /*   1K internal RAM block 1 */
  LOCAL:  org=0x00300000, len=0x7D000000 /*  ~2G external RAM local   */
  GLOBAL: org=0x80000000, len=0x80000000 /*   2G external RAM global  */
/* modules TIM40 constructeur AITA modele CMTP40 */
  RAML:   org=0x00300000, len=0x00020000 /* 128K external RAM local  */
  RAMG:   org=0x80000000, len=0x00020000 /* 128K external RAM global */
}
SECTIONS{
 .vect:   >RAML align(512) {IVT=.; .+=0x40;} /* Interrupt Vector Table */
 .text:   >RAML /* code */
 .data:   >RAMG /* data */
 .cinit:  >RAML /* C initialization tables */
 .const:  >RAMG /* C constants */
 .stack:  >RAM0 /* C call stack */
 .sysmem: >RAM1 /* C heap for malloc */
 .bss:    >RAMG block(0x10000) /* uninitialized variables */
 .syndex0:>RAM0 /* user specified memory bank 0 */
 .syndex1:>RAM1 /* user specified memory bank 1 */
 .syndex2:>RAML /* user specified memory bank 2 */
 .syndex3:>RAMG /* user specified memory bank 3 */
}